$ whoami
Lucas Tidy
$ about --me
Third-year Computer Engineering student at UBC with interests spanning embedded systems, digital design, and full-stack development. I enjoy tackling problems across the hardware-software stack. Whether it's designing PCBs and writing firmware in C, implementing digital logic on FPGAs, or building cloud-based web applications. Currently diving deeper into FPGA verification, learning UVM and applying it to past and current personal projects. Always looking for opportunities to learn, build, and collaborate on challenging technical problems.
$ cat --projects
Projects
Pressure Sensor PCB and Enclosure Design
Designed and assembled a custom RP2040-based PCB with dual DPS368 pressure sensors, developed bare-metal C firmware, and created a gasket-sealed enclosure for accurate airflow measurements.
Key Achievements:
- Developed bare-metal C firmware using the Pico SDK to poll sensors over I2C and expose readings through a shared register interface.
- Verified and refined PCB design in KiCAD, improving signal integrity and sensor accuracy.
- Created a gasket-sealed airtight enclosure in Autodesk Inventor with venturi manifold ports for stable airflow calibration.
Mario Kart 8 Deluxe Leaderboard Web App
Developed a Flask-based leaderboard web app where players can upload and compare time trial records for Mario Kart 8 Deluxe, with backend data stored in PostgreSQL.
Key Achievements:
- Built using Flask and PostgreSQL for a scalable backend.
- Designed responsive UI with modular Jinja2 templates and custom CSS components.
- Implemented user authentication, leaderboard rendering, and screenshot-based validation.
- Deployed on AWS Elastic Beanstalk using Docker and automated CI/CD via GitHub Actions.
F1TENTH Autonomous Car
Developed a ROS2-based control stack for a 1/10th scale autonomous F1 car, integrating LiDAR and depth cameras for real-time perception and control.
Key Achievements:
- Achieved 0% crash rate and 100% obstacle detection in closed-loop testing.
- Implemented PID wall following, gap following, and automatic emergency braking using Python and ROS2.
- Developed a sensor fusion pipeline combining LiDAR and depth camera data via NumPy and OpenCV.
- Built a ROS2 lap-detection node using visual similarity for sub-second accurate lap timing.
Audio Signal Verification with UVM - Current Project
Learning UVM by building a simple RTL module that computes per-frame peak and RMS from an audio stream and triggers interrupts on threshold exceed using SystemVerilog.
Key Achievements:
- AXI-Stream input interface with 16-bit signed samples
- Real-time peak and RMS calculation with programmable thresholds
- Interrupt output when thresholds exceeded
- RTL + UVM-style testbench including constrained-random stimulus, scoreboard comparisons, functional coverage, and SVA assertions
$ contact --info
Let's Connect
$ location --current
$ contact --email
lucastidyy@gmail.com$ cat resume.pdf
Download Resume$ ls ./social-links
$ send-message